1. Field of Invention
The present invention relates to a semiconductor device, and particularly to a non-volatile memory (NVM), a manufacturing method and an operating method thereof.
2. Description of the Related Art
Among various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used in personal computers and electronic equipment. Data can be stored, read out or erased from the EEPROM many times and stored data are retained even after power supplying the devices is cut off.
The floating gate and the control gate in a typical EEPROM are made of doped polysilicon. By applying bias voltages to the control gate and a source/drain region thereof, the EEPROM operates. When erasing data in the EEPROM however, it is likely to over-erase, which leads to misjudgment of data. In addition, to follow the trend of high integrity in the current semiconductor industry, the memory size becomes smaller, with shorter channel length. Therefore, when programming the memory cell, an abnormal punch-through phenomenon occurs between a drain region and a source region, which has an adverse impact on the electrical performance of the memory.
For other non-volatile memories of the prior art, a silicon nitride layer, instead of a polysilicon floating gate, is used to form an ONO composite layer (oxide-nitride-oxide composite layer). Such a device is referred to as a SONOS device (silicon-oxide-nitride-oxide-silicon device). Since the silicon nitride is able to capture electrons, the electrons injected in the silicon nitride layer would not be evenly distributed in the whole layer. Instead, the injected electrons concentrate on local regions of the silicon nitride layer. By changing the applied voltages on the control gate and the source/drain regions at both sides of the control gate, at the left side and the right side of a memory in a layer made of single silicon nitride material, 1-bit is stored, respectively. In this way, the non-volatile memory for storing 2 bits/cell is formed.
The memory cells still face the challenge of higher integrity of memory cell and shorter channel length. Under such situation, the two 1-bits of a memory cell would affect each other, so that two charge-distribution curves corresponding to the two 1-bits get broader, even merge together to generate a so-called second bit effect. As a result, when erasing data, the distribution curve formed by injected hot holes in the silicon nitride layer is not able to overlap with the electron-distribution curve, which leads to incomplete erasing and longer erasing time. This problem results in a slow operating speed and poor efficiency, even lower reliability.
It can be concluded that a non-volatile memory capable of storing multiple bits in a single memory cell without the second bit effect, over-erase and punch-through is desired in the related semiconductor manufactures.